Professional Profile

Senior ASIC and SoC physical designer with more than 20 years of international, hands-on experience in the Semiconductor industry. Expert knowledge in IC analog physical design, comprehensively covering the following areas

  • Toplevel and module level floorplanning and physical design architecture
  • Full custom layout in CMOS , BCD, bipolar and HV CMOS
  • Top and module level verification
  • Toplevel responsibility, project management and team leadership 

Designs and Applications 

  • Automotive/industrial electronics
    • Physical design of high pressure and temp. Sensor IP in a BCD 130 nm trench technology
    • Physical design of a electronic steering control IC in a BCD 130 nm trench technology
    • Project management and team leadership for physical design of a dynamic stability control chip in a BCD TSMC 130nm process
    • Physical design of EEPROM periphery
    • Physical design of door module driver chip up to 10 Amp
    • Physical design of glow plug driver chip 
  • Communication electronics
    • Carried out physical design of several mixed signal analog blocks using customer internal analog and mixed signal design flow. Extensive use of Cadence XL, VCAR tools as well as Assura and Calibre for verification. 
  • Consumer electronics
    • Full custom layout for power management block including LDO, Boost Converter and DC/DC Buck converter in a BCD 130 nm trench isolation technology
    • Toplevel responsibility and layout development of a low power DC/DC buck converter with high frequent switching power mos, up to 10 A stable 1.1 V output
    • Project management and team leadership of a high frequency hard disk head amplifier up to 3 GHz
  • Chip card
    • Physical design of high encryption chip with coreless power supply and code protection
  • Miscellaneous
    • Physical design of high power transistors up to 10A in some power technologies with current density check, via R3D Silicon Frontline tool


Software Tools and Production Technologies 

  • Experience in CMOS, BCD, HV CMOS and bipolar
    • down to a minimum Gate length of 65 nm in CMOS technologies
    • Up to 100 V in BCD and HV CMOS technologies
  • All relevant CADENCE tools 



German               Mother Tongue

English                 Fluent